System-on-Chip

F. Bensaali, A. Amira and R. Sotudeh, "Floating-Point Matrix Product on FPGA ", The ACS/IEEE International Conference on Computer Systems and Applications, Amman, Jordan , May 2007.
F. Bensaali, A. Amira and S. Chandrasekaran, "Power Modeling and Efficient FPGA Implementation of Color Space Conversion ", The 13th IEEE International Conference on Electronics, Circuits and Systems, France, December 2006.
C. M. Tang and J. Xu, "Accurate Extraction of Contour Information from the Cleavage of Neural Stem Cells", International Conference on BioMedical and Pharmaceutical Engineering 2006 (ICBPE2006), Singapore, December 2006.
F. Bensaali and A. Amira, "An FPGA Based Parallel Matrix Multiplier for 3D Affine Transformations", IEE Proceedings on Vision, Image and Signal Processing-Special Issue on Rapid Prototyping of Signal Processing Algorithms, Vol. 153, Issue 6, pp. 739-746, December. 2006.
A. Amira, F. Bensaali, I. S. Uzun and A. Ahmedsaid, "Matrix Algorithm Cores Generator on Reconfigurable Hardware for Image Processing", The Military and Aerospace Applications of Programmable Logic Devices and Technologies International Conference (MAPLD’06), Washington, D.C. USA, September 2006.
Z. Ahmad, R. Sotudeh and J. Xu, "Co-operative Intelligent Memory", The 6th International Conference on Computer and Communication Engineering, Kuala Lumpur, Malaysia, May 2006.
J. Xu, A. M. Ariyaeeinia and R. Sotudeh, "User Voice Identification on FPGA", Edition on Perspectives in Pervasive Computing, IEE proceedings, November 2005.
J. Xu, A. M. Ariyaeeinia and R. Sotudeh, "Migrate Levinson-Durbin Based Linear Predictive Coding Algorithm into FPGAs", The 12th International Conference on Electronics, Circuits and Systems, Tunisia, December 2005.
J. Xu, A. M. Ariyaeeinia and R. Sotudeh, " Pre-processing Speech Signals in FPGAs", The 6th International Conference on ASIC, China, October 2005.
F. Bensaali and A. Amira, "Accelerating Color Space Conversion on Reconfigurable Hardware", Image and Vision Computing (Elsevier), Vol. 23, Issue 11, pp. 935-942, October 2005.
S. Chandrasekaran, A. Amira and F. Bensaali, "FPGA Implementation of Reduced Bit Plane Motion Estimation", The Military and Aerospace Applications of Programmable Logic Devices and Technologies International Conference (MAPLD’05), Washington, D.C. USA, September 2005. (Selected and re-published at Celoxica’s company website)
Z. Ahmad, J. Xu and R. Sotudeh, "Nexar as a Development Enviroment for Cooperative-Pseudo-Intelligent-Memory", Customer Conference, UK, September 2005.
F. Bensaali and A. Amira, "Floating-Point Matrix Multiplication for 3D Affine Transformations on Reconfigurable Hardware", IEEE International Conference on Computer Systems and Information Technology (ICSIT 2005), pp. 689-695, Algiers, Algeria, July 2005.
J. Xu and R. Sotudeh, "Memory Management in Output-Buffering Packet-Switch Design", The 7th International Symposium on Signals Circuits and Systems, Romania, July 2005.
F. Bensaali, A. Amira and A. Bouridane, "Accelerating Matrix Product on Reconfigurable Hardware for Image Processing Applications", IEE Proceedings on Circuits, Devices and Systems, Vol. 152, Issue 3, pp. 236-246, June 2005.